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JEDEC Announces Publication of DDR4 Standard

Finally comes the long awaited initial publication of the widely-anticipated Synchronous DDR4 (Double Data Rate 4) standard.

DDR4 offers a range of innovative features designed to enable high speed operation and broad applicability in a variety of applications including servers, laptops, desktop PCs and consumer products. In addition to the advantages described later in this release, the new technology has been defined with a goal of simplifying migration and enabling adoption of an industry-wide standard.

The per-pin data rate for DDR4 is specified as 1.6 giga transfers per second to an initial maximum objective of 3.2 giga transfers per second. With DDR3 exceeding its original targeted performance of 1.6 GT/s, it is likely that higher performance speed grades will be added in a future DDR4 update. Other DDR4 attributes tightly intertwined with the planned speed grades, enabling device functionality as well as application adoption, include: a pseudo open drain interface on the DQ bus, a gear down mode for 2,667 MT/s per DQ and beyond, bank group architecture, internally generated VrefDQ and improved training modes.

The DDR4 architecture is an 8n prefetch with two or four selectable bank groups. This design will permit the DDR4 memory devices to have separate activation, read, write or refresh operations underway in each unique bank group. This concept will also improve overall memory efficiency and bandwidth, especially when small memory granularities are used. More information about additional features may be found on the JEDEC website.

In addition, DDR4 has been designed in such a way that stacked memory devices may prove to be a key factor during the lifetime of the technology, with stacks of up to 8 memory devices presenting only a single signal load.

But what does all that mean to the end user, or even to someone who doesn't understand a word of what has just been said? well the long and short of it is that in a couple of years there will be new motherboards with support for a new type of ram module, the result of this will be potentially higher performance and lower power consumption and less power in more power out is always a good thing for computer components.

Joe Macri, Chairman of JEDEC's JC-42.3 Subcommittee for DRAM Memories, said: "The publication of the JEDEC DDR4 standard represents the culmination of years of dedicated effort by memory device, system, component and module producers worldwide. The new standard will enable next generation systems to achieve greater performance, significantly increased packaging density and improved reliability - with lower power consumption."

"The industry has been looking forward to the publication of this standard for some time," noted Desi Rhoden, Chairman JC-42 Memory Committee and Executive VP Montage Technology. "The current publication will provide early adopters with the critical information required to utilize the emerging DDR4 devices. Subsequent publications are planned to address material not yet finalized in time for this publication. As with all JEDEC standardization activities, industry participation is highly valued – companies interested in participating in JEDEC may visit the JEDEC website at or call 703-907-7560 for more information."

JEDEC DDR4 (JESD79-4) has been defined to provide higher performance, with improved reliability and reduced power, thereby representing a significant achievement relative to previous DRAM memory technologies. The new DDR4 standard is available for free download from the JEDEC website at